IS43LR16160H-6BLI

Mfr. #:: IS43LR16160H-6BLI
製造商:: ISSI
描述:: DRAM 256M, 1.8V, Mobile DDR, 16Mx16, 166Mhz, 90 ball BGA (8mmx10mm) RoHS, IT
生命週期:: 製造商新產品
數據表:: IS43LR16160H-6BLI 數據表
交貨:: DHL FedEx Ups TNT EMS
支付:: T/T Paypal Visa MoneyGram Western Union
ECAD Model:
更多信息:: IS43LR16160H-6BLI 更多信息

產品屬性
屬性值

製造商：: 國際空間站

產品分類：: 動態隨機存取存儲器

RoHS：: Y

類型：: SDRAM 移動 - DDR

數據總線寬度：: 16 bit

組織：: 16 M x 16

包裝/案例：: BGA-60

內存大小：: 256 Mbit

最大時鐘頻率：: 166 MHz

訪問時間：: 6 ns

電源電壓 - 最大值：: 1.95 V

電源電壓 - 最小值：: 1.7 V

電源電流 - 最大值：: 55 mA

最低工作溫度：: - 40 C

最高工作溫度：: + 85 C

系列：: IS43LR16160H

品牌：: 國際空間站

安裝方式：: 貼片/貼片

濕氣敏感：: 是的

產品類別：: 動態隨機存取存儲器

出廠包裝數量：: 300

子類別：: 內存和數據存儲

Tags: IS43LR16160H, IS43LR161, IS43LR1, IS43LR, IS43L, IS43, IS4

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

IS43LR16160H-6BLI 評級和評論

W***g

Looks ok , not tested yet

2019-09-18

V***v

Alas so the goods and did not see the description to give.

2019-05-18

M***v

thank you very much

2019-05-20

IS43LR16160H-6BLI 更多信息

Mobile DDR SDRAM: ISSI Mobile DDR SDRAM is organized as 4 banks of 16,777,216 words x 16 bits and uses a double-data-rate architecture to achieve high-speed operation. The Data Input/Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ISSI Mobile DDR SDRAM offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

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