LTC4313IDD-3#TRPBF

Mfr. #:: LTC4313IDD-3#TRPBF
製造商:: Analog Devices Inc.
描述:: Interface - Signal Buffers, Repeaters 2-Wire Bus Bufs w/ Hi N Margin
生命週期:: 製造商新產品
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ECAD Model:
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產品屬性
屬性值

製造商：: 模擬設備公司

產品分類：: 接口 - 信號緩衝器、中繼器

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: DFN-8

打包：: 捲軸

系列：: LTC4313

品牌：: 模擬設備公司

產品類別：: 信號緩衝器、中繼器

出廠包裝數量：: 2500

子類別：: 接口 IC

Tags: LTC4313ID, LTC4313I, LTC4313, LTC431, LTC43, LTC4, LTC

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

LTC4313IDD-3#TRPBF 描述

***ark: Ms-Bus Buffers 2-Wire Bus Buffer With High Noise Margin

***i-Key: IC ACCELERATOR I2C HOTSWAP 8DFN

***log Devices: The LTC4313 is a hot swappable 2-wire bus buffer that provides bidirectional buffering while maintaining a low offset voltage and high noise margin up to 0.3 • VCC. The high noise margin allows the LTC4313 to be interoperable with devices that drive a high VOL (>0.4V) and allows multiple LTC4313s to be cascaded. The LTC4313-1 and LTC4313-2 support level translation between 3.3V and 5V busses. In addition to these voltages, the LTC4313-3 also supports level translation to 1.5V, 1.8V and 2.5V. During insertion, the SDA and SCL lines are pre-charged to 1V to minimize bus disturbances. Connection is established between the input and output after ENABLE is asserted high and a stop bit or bus idle condition has been detected on the SDA and SCL pins. If both data and clock are not simultaneously high at least once in 45ms, the input is disconnected from the output. Up to 16 clock pulses are subsequently generated to free the stuck bus. Rise time accelerators (RTAs) provide pull-up currents on SDA and SCL rising edges to meet rise time specifications in heavily loaded systems. The RTAs are configured as slew limited switches in the LTC4313-1 and 2.5mA current sources in the LTC4313-2. The LTC4313-3 does not have RTAs. Applications Capacitance Buffers/Bus Extender Live Board Insertion Telecommunications Systems Including ATCA Level Translation PMBus Servers

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