SN74ALVCH16903DLR

Mfr. #:: SN74ALVCH16903DLR
描述:: IC UNIV BUS DVR 12BIT 56SSOP
生命週期:: 製造商新產品
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產品屬性
屬性值

製造商: 德州儀器

產品分類: 邏輯 - 通用總線功能

系列: 74ALVCH

打包: 捲帶 (TR) 替代包裝

包裝盒: 56-BSSOP (0.295", 7.50mm Width)

工作溫度: 0°C ~ 70°C

安裝型: 表面貼裝

電壓供應: 2.3 V ~ 3.6 V

供應商-設備-包: 56-SSOP

電路數: 12-Bit

輸入數: -

電流輸出高低: 24mA, 24mA

邏輯型: 通用總線驅動程序

Tags: SN74ALVCH16903, SN74ALVCH1690, SN74ALVCH169, SN74ALVCH1, SN74ALVCH, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ALVCH16903DLR 描述

***i-Key: IC UNIV BUS DVR 12BIT 56SSOP

***as Instruments: This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation. The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR\ output, which is produced one cycle after APAR, is open drain. MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN\) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN\ is high, only data set up at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN\ serves a dual purpose; it acts as a normal data bit and also enables YERR\ data to be clocked into the YERR\ output register. When used as a single device, parity output enable (PAROE\) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE\ is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used in pairs and PAROE\ is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903. A buffered output-enable (OE\) input can be used to place the 24 outputs and YERR\ in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the device. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16903 is characterized for operation from 0C to 70C.

Market price

型號	描述	庫存	價格
SN74ALVCH16903DLR DISTI # SN74ALVCH16903DLR-ND	IC UNIV BUS DVR 12BIT 56SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ALVCH16903DLR DISTI # 595-SN74ALVCH16903LR	Bus Transceivers 16-Bit Bus Trnscvrs With 3-State Outputs RoHS: Compliant	0
SN74ALVCH16903DLR	Bus Driver, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56 RoHS: Compliant	1000	1000:$16.0500 500:$16.9000 100:$17.5900 25:$18.3500 1:$19.7600

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