CDC925DLRG4

CDC925DLRG4
Mfr. #:
CDC925DLRG4
描述:
Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr
生命週期:
製造商新產品
數據表:
CDC925DLRG4 數據表
交貨:
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ECAD Model:
更多信息:
CDC925DLRG4 更多信息 CDC925DLRG4 Product Details
產品屬性
屬性值
製造商:
德州儀器
產品分類:
時鐘合成器/抖動清除器
最大輸入頻率:
14.8 MHz
電源電壓 - 最大值:
3.465 V
電源電壓 - 最小值:
2.375 V
最低工作溫度:
0 C
最高工作溫度:
+ 85 C
安裝方式:
貼片/貼片
包裝/案例:
SSOP-56
打包:
捲軸
高度:
2.59 mm
長度:
18.41 mm
類型:
PLL 時鐘合成器
寬度:
7.49 mm
品牌:
德州儀器
工作電源電壓:
2.5 V, 3.3 V
產品類別:
時鐘合成器/抖動清除器
出廠包裝數量:
1
子類別:
時鐘和定時器 IC
單位重量:
0.024508 oz
Tags
CDC925D, CDC925, CDC92, CDC9, CDC
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC 133-MHZ CLOCK SYNTH 56-SSOP
***ark
IC, CLOCK SYNTHESIZER, 133MHZ, SSOP-56; Clock IC Type:Clock Synthesizer / Driver; Frequency:133MHz; No. of Outputs:19; Supply Current:12mA; Supply Voltage Range:3.135V to 3.465V, 2.375V to 2.625V; Digital IC Case Style:SSOP ;RoHS Compliant: Yes
***as Instruments
The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100\. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN\ terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP\ or CPU_STOP\, the outputs operate normally. With a low-level applied to the PCI_STOP\ or CPU_STOP\ terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100\ control input. The PCI bus frequency is fixed to 33MHz. Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
型號 描述 庫存 價格
CDC925DLRG4
DISTI # CDC925DLRG4-ND
IC 133-MHZ CLOCK SYNTH 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    CDC925DLRG4
    DISTI # N/A
    Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr0
      圖片 型號 描述
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      OMO.#: OMO-CDC925DLR-TEXAS-INSTRUMENTS

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      Mfr.#: CDC925DLG4

      OMO.#: OMO-CDC925DLG4-TEXAS-INSTRUMENTS

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      Mfr.#: CDC925DLRG4

      OMO.#: OMO-CDC925DLRG4-TEXAS-INSTRUMENTS

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      CDC925DL

      Mfr.#: CDC925DL

      OMO.#: OMO-CDC925DL-TEXAS-INSTRUMENTS

      Clock Synthesizer / Jitter Cleaner 133MHz Clk Synth
      CDC924DL

      Mfr.#: CDC924DL

      OMO.#: OMO-CDC924DL-TEXAS-INSTRUMENTS

      Clock Synthesizer / Jitter Cleaner 133MHz Clk Synth
      可用性
      庫存:
      Available
      訂購:
      5500
      輸入數量:
      CDC925DLRG4的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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