SN65LVDS352PWR

Mfr. #:: SN65LVDS352PWR
描述:: Bus Receivers Quad LVDS Receiver
生命週期:: 製造商新產品
數據表:: SN65LVDS352PWR 數據表
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更多信息:: SN65LVDS352PWR 更多信息 SN65LVDS352PWR Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 總線接收器

RoHS：: Y

接收器數量：: 4 Receiver

接收器信號類型：: 微分

電源電壓 - 最小值：: 3 V

電源電壓 - 最大值：: 3.6 V

工作電源電流：: 20 mA

最低工作溫度：: - 40 C

最高工作溫度：: + 85 C

包裝/案例：: TSSOP-24

打包：: 捲軸

數據速率：: 560 Mb/s

品牌：: 德州儀器

安裝方式：: 貼片/貼片

濕氣敏感：: 是的

產品類別：: 總線接收器

出廠包裝數量：: 1

子類別：: 邏輯 IC

單位重量：: 0.007478 oz

Tags: SN65LVDS35, SN65LVDS3, SN65LVDS, SN65LVD, SN65LV, SN65L, SN65, SN6

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN65LVDS352PWR 描述

***i-Key: IC DIFF RECEIVER QUAD HS 24TSSOP

***ser: LVDS/M-LVDS/ECL/CML Quad LVDS Receiver

***as Instruments: The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The 348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The 352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110- line termination resistor. These receivers also provide 3x the standards minimum common-mode noise voltage tolerance. The 4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface. Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than 50 mV over the full input common-mode voltage range. The receiver inputs can withstand 15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The receivers also include a (patent-pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space requirements and parts count by eliminating the need for a separate termination resistor. This can also improve signal integrity at the receiver by reducing the stub length from the line termination to the receiver. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from 40C to 85C.

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