CD74HCT161E

Mfr. #:: CD74HCT161E
描述:: Counter ICs Sync 4-Bit Binary
生命週期:: 製造商新產品
數據表:: CD74HCT161E 數據表
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產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器 IC

RoHS：: Y

安裝方式：: 通孔

包裝/案例：: PDIP-16

計數器類型：: 二進制

邏輯系列：: HCT

位數：: 4 bit

計數方法：: 異步

計數順序：: 向上

工作電源電壓：: 4.5 V to 5.5 V

最低工作溫度：: - 55 C

最高工作溫度：: + 125 C

系列：: CD74HCT161

打包：: 管子

功能：: 櫃檯

工作溫度範圍：: - 55 C to + 125 C

輸出電流：: +/- 4 mA

品牌：: 德州儀器

產品類別：: 計數器 IC

出廠包裝數量：: 25

子類別：: 計數器 IC

單位重量：: 0.033570 oz

Tags: CD74HCT161E, CD74HCT161, CD74HCT16, CD74HCT1, CD74HCT, CD74HC, CD74H, CD74, CD7

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD74HCT161E 評級和評論

A***v

Very slow shipping .. Me and my friends will no longer use the services of such a store...

2019-07-15

R***v

I got everything, everything is fine

2019-03-01

P***p

Delivery was fast plus package is in good condition

2019-07-03

CD74HCT161E 描述

***as Instruments: High Speed CMOS Logic 4-Bit Binary Counter with Asynchronous eset 16-PDIP -55 to 125

***ical: Counter Single 4-Bit Sync Binary UP 16-Pin PDIP Tube

***ment14 APAC: IC, 4BIT BINARY COUNTER, ASYNC, DIP-16

***ark: LOGIC, 4BIT BINARY COUNTER, 16DIP

***ser: Logic - Counters Sync 4-Bit Binary

***as Instr.: The HC161, HCT161, HC163, and HCT163 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The HC161 and HCT161 are asynchronous reset decade and binary counters, respectively; the HC163 and HCT163 devices are decade and binary counters, respectively, that are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock.

***as Instruments Inc.: A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met).

***AS INTRUMENTS: All counters are reset with a low level on the Master Reset input, MR. In the HC163 and HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met.

***AS INSTRUMENT: Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE\, PE and TE inputs (and the clock input, CP, in the HC161 and HCT161 types).

***AS INSTRUM: If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.

***AS INSTRUMEN: The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.

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