SN74ALVCH16271DLR

Mfr. #:: SN74ALVCH16271DLR
描述:: IC MULTIPLEXED BUS EXCH 56SSOP
生命週期:: 製造商新產品
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Tags: SN74ALVCH16271, SN74ALVCH1627, SN74ALVCH162, SN74ALVCH1, SN74ALVCH, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ALVCH16271DLR 描述

***i-Key: IC MULTIPLEXED BUS EXCH 56SSOP

***as Instruments: This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors. A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE\) inputs are low. The select (SEL\) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA\, OEB\). To ensure the high-impedance state during power up or power down, the output enables should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Market price

型號	描述	庫存	價格
SN74ALVCH16271DLR DISTI # SN74ALVCH16271DLR-ND	IC MULTIPLEXED BUS EXCH 56SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ALVCH16271DLR DISTI # 595-74ALVCH16271DLR	Universal Bus Functions 12B To 24B Multplx Bus Exchngr RoHS: Compliant	0

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