CD74HC40103M96

Mfr. #:: CD74HC40103M96
描述:: Counter ICs Hi-Sp CMOS Logic 8-Stg Sync Down
生命週期:: 製造商新產品
數據表:: CD74HC40103M96 數據表
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更多信息:: CD74HC40103M96 更多信息 CD74HC40103M96 Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器 IC

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: SOP-16

計數器類型：: 二進制

邏輯系列：: 慧聰

位數：: 8 bit

計數順序：: 向下

工作電源電壓：: 2 V to 6 V

最低工作溫度：: - 55 C

最高工作溫度：: + 125 C

系列：: CD74HC40103

打包：: 捲軸

功能：: 櫃檯

工作溫度範圍：: - 55 C to + 125 C

輸出電流：: +/- 5.2 mA

品牌：: 德州儀器

產品類別：: 計數器 IC

出廠包裝數量：: 2500

子類別：: 計數器 IC

單位重量：: 0.004998 oz

Tags: CD74HC40103M9, CD74HC40103M, CD74HC40103, CD74HC4010, CD74HC401, CD74HC40, CD74HC4, CD74HC, CD74H, CD74, CD7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD74HC40103M96 評級和評論

D***c

SRB

received sensor, not tested

2019-06-10

G***p

Came for two weeks, all the norms.

2019-04-26

V***n

Excellent resistors

2019-01-30

CD74HC40103M96 描述

***as Instruments: High Speed CMOS Logic 8-Stage Synchronous Down Counters 16-SOIC -55 to 125

***ical: Counter Single 8-Bit Sync/Async Binary Down 16-Pin SOIC T/R

***ark: 8 STAGE BINARY DOWN COUNTER, SOIC-16

***ser: Logic - Counters Hi-Sp CMOS Logic 8-Stg Sync Down

***AS INSRUMENTS: The HC40103 and CD74HCT40103 are manufactured with high speed silicon gate technology and consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the TC\ output are active-low logic.

***ASIN: In normal operation, the counter is decremented by one count on each positive transition of the CLOCK (CP). Counting is inhibited when the TE\ input is high. The TC\ output goes low when the count reaches zero if the TE\ input is low, and remains low for one full clock period.

***TEXAS: When the PE\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE\ input. When the PL\ input is low, data at the P0-P7 inputs are asynchronously forced into the counter regardless of the state of the PE\, TE\, or CLOCK inputs. Input P0-P7 represent a single 8-bit binary word for the 40103. When the MR input is low, the counter is asynchronously cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

***as Instr.: If all control inputs except TE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long.

***AS INSRUMENT: The 40103 may be cascaded using the TE\ input and the TC\ output, in either a synchronous or ripple mode. These circuits possess the low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits and can drive up to 10 LSTTL loads.

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