SN74ALVC7803-25DL

SN74ALVC7803-25DL
Mfr. #:
SN74ALVC7803-25DL
描述:
FIFO 16-Bit Buffer/Driver With 3-State Outputs
生命週期:
製造商新產品
數據表:
SN74ALVC7803-25DL 數據表
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ECAD Model:
更多信息:
SN74ALVC7803-25DL 更多信息 SN74ALVC7803-25DL Product Details
產品屬性
屬性值
製造商:
德州儀器
產品分類:
先進先出
RoHS:
Y
數據總線寬度:
18 bit
巴士方向:
單向
內存大小:
9 kbit
計時類型:
同步
組織:
512 k x 18
電路數量:
2
最大時鐘頻率:
40 MHz
訪問時間:
15 ns
電源電壓 - 最大值:
3.6 V
電源電壓 - 最小值:
3 V
電源電流 - 最大值:
0.04 mA
最低工作溫度:
0 C
最高工作溫度:
+ 70 C
包裝/案例:
SSOP-56
打包:
管子
高度:
2.59 mm
寬度:
7.49 mm
品牌:
德州儀器
安裝方式:
貼片/貼片
工作電源電壓:
3 V to 3.6 V
產品類別:
先進先出
出廠包裝數量:
1
子類別:
內存和數據存儲
單位重量:
0.024508 oz
Tags
SN74ALVC7803-2, SN74ALVC7803, SN74ALVC780, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 512 x 18 56-Pin SSOP Tube
***i-Key
IC 512X18 SYNC FIFO MEM 56-SSOP
***as Instruments
The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink small-outline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when ,, and are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the ,, and levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.
型號 描述 庫存 價格
SN74ALVC7803-25DL
DISTI # 296-5162-5-ND
IC 512X18 SYNC FIFO MEM 56-SSOP
RoHS: Compliant
Min Qty: 80
Container: Tube
Limited Supply - Call
    SN74ALVC7803-25DLR
    DISTI # SN74ALVC7803-25DLR-ND
    IC MEMORY FIFO 512X18 56-SSOP
    RoHS: Compliant
    Min Qty: 1000
    Container: Tape & Reel (TR)
    Limited Supply - Call
      SN74ALVC7803-25DL
      DISTI # 595-SN74ALVC780325DL
      FIFO 16-Bit Buffer/Driver With 3-State Outputs
      RoHS: Compliant
      0
        SN74ALVC7803-25DLR
        DISTI # N/A
        FIFO 512 X 18 CLOCKED FIFO0
          SN74ALVC7803-25DLFIFO, 512X18, 15ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant
          2456
          • 1000:$6.9300
          • 500:$7.3000
          • 100:$7.6000
          • 25:$7.9300
          • 1:$8.5300
          SN74ALVC7803-25DLRFIFO, 512X18, 15ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant
          1000
          • 1000:$6.9300
          • 500:$7.3000
          • 100:$7.6000
          • 25:$7.9300
          • 1:$8.5300
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          Universal Bus Functions 12-24bit
          可用性
          庫存:
          Available
          訂購:
          2500
          輸入數量:
          SN74ALVC7803-25DL的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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