74ABT16600DGGRG4

Mfr. #:: 74ABT16600DGGRG4
描述:: IC UNIV BUS TXRX 18BIT 56TSSOP
生命週期:: 製造商新產品
數據表:: 74ABT16600DGGRG4 數據表
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更多信息:: 74ABT16600DGGRG4 更多信息 74ABT16600DGGRG4 Product Details

產品屬性
屬性值

Tags: 74ABT1660, 74ABT166, 74ABT16, 74ABT1, 74ABT, 74AB, 74A

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

74ABT16600DGGRG4 描述

***i-Key: IC UNIV BUS TXRX 18BIT 56TSSOP

***as Instruments: These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA\, and CLKENBA\. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16600 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT16600 is characterized for operation from -40C to 85C

Market price

型號	描述	庫存	價格
74ABT16600DGGRG4 DISTI # 74ABT16600DGGRG4-ND	IC UNIV BUS TXRX 18BIT 56TSSOP RoHS: Compliant Min Qty: 2000 Container: Tape & Reel (TR)	Limited Supply - Call
74ABT16600DGGRG4 DISTI # 595-74ABT16600DGGRG4	Universal Bus Functions 18B Uni Bus Xceivers RoHS: Compliant	0

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