SN74ACT7813-20DLR

Mfr. #:: SN74ACT7813-20DLR
描述:: FIFO 64 x 18 synchronous FIFO memory
生命週期:: 製造商新產品
數據表:: SN74ACT7813-20DLR 數據表
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更多信息:: SN74ACT7813-20DLR 更多信息 SN74ACT7813-20DLR Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 先進先出

RoHS：: Y

包裝/案例：: SSOP-56

打包：: 捲軸

品牌：: 德州儀器

安裝方式：: 貼片/貼片

工作電源電壓：: 4.5 V to 5.5 V

產品類別：: 先進先出

出廠包裝數量：: 1

子類別：: 內存和數據存儲

單位重量：: 0.024508 oz

Tags: SN74ACT7813-2, SN74ACT7813, SN74ACT781, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7

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Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT7813-20DLR 描述

***et: FIFO Mem Sync Dual Width Bi-Dir 64 x 18 56-Pin SSOP T/R

***i-Key: IC CLOCKED FIFO 64X18 56-SSOP

***as Instruments: The SN74ACT7813 is a 64-word 18-bit FIFO suited for buffering asynchronous datapaths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7813 is characterized for operation from 0C to 70C.

Market price

型號	描述	庫存	價格
SN74ACT7813-20DLR DISTI # SN74ACT7813-20DLR-ND	IC CLOCKED FIFO 64X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ACT7813-20DLR DISTI # 595-SN74ACT781320DLR	FIFO 64 x 18 synchronous FIFO memory RoHS: Compliant	0
SN74ACT7813-20DLR	FIFO, 64X18, 13ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	1000	1000:$6.9300 500:$7.3000 100:$7.6000 25:$7.9300 1:$8.5300

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