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SN74ACT7805-20DL

SN74ACT7805-20DL
Mfr. #:
SN74ACT7805-20DL
描述:
FIFO 256 x 18 synchronous FIFO memory
生命週期:
製造商新產品
數據表:
SN74ACT7805-20DL 數據表
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SN74ACT7805-20DL 更多信息 SN74ACT7805-20DL Product Details
產品屬性
屬性值
製造商：
德州儀器
產品分類：
先進先出
RoHS：
Y
數據總線寬度：
18 bit
巴士方向：
單向
內存大小：
4.5 kbit
計時類型：
同步
組織：
256 k x 18
電路數量：
2
最大時鐘頻率：
50 MHz
訪問時間：
13 ns
電源電壓 - 最大值：
5.5 V
電源電壓 - 最小值：
4.5 V
電源電流 - 最大值：
0.4 mA
最低工作溫度：
0 C
最高工作溫度：
+ 70 C
包裝/案例：
SSOP-56
打包：
管子
高度：
2.59 mm
寬度：
7.49 mm
品牌：
德州儀器
安裝方式：
貼片/貼片
工作電源電壓：
4.5 V to 5.5 V
產品類別：
先進先出
出廠包裝數量：
1
子類別：
內存和數據存儲
單位重量：
0.024508 oz
Tags
SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SYNC FIFO MEM 256X18 56-SSOP
***as Instruments
The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.
型號 描述 庫存 價格
SN74ACT7805-20DL
DISTI # 296-4456-5-ND		IC SYNC FIFO MEM 256X18 56-SSOP
RoHS: Compliant
Min Qty: 40
Container: Tube		Limited Supply - Call
    SN74ACT7805-20DLR
    DISTI # SN74ACT7805-20DLR-ND    		IC CLOCKED FIFO 256X18 56-SSOP
    RoHS: Compliant
    Min Qty: 1000
    Container: Tape & Reel (TR)    		Limited Supply - Call
      SN74ACT7805-20DL
      DISTI # 595-SN74ACT7805-20DL      		FIFO 256 x 18 synchronous FIFO memory
      RoHS: Compliant      		0
        SN74ACT7805-20DLR
        DISTI # 595-SN74ACT780520DLR        		FIFO 256 x 18 synchronous FIFO memory
        RoHS: Compliant        		0
          SN74ACT7805-20DLFIFO, 256X18, 13ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant          		1717
          • 1000:$15.7100
          • 500:$16.5400
          • 100:$17.2200
          • 25:$17.9600
          • 1:$19.3400
          SN74ACT7805-20DLRFIFO, 256X18, 13ns, Synchronous, CMOS, PDSO56
          RoHS: Compliant          		36750
          • 1000:$15.7100
          • 500:$16.5400
          • 100:$17.2200
          • 25:$17.9600
          • 1:$19.3400
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          可用性
          庫存:
          Available
          訂購:
          3500
          輸入數量:
          SN74ACT7805-20DL的當前價格僅供參考，如果您想獲得最優惠的價格，請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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