CD4031BPWR

Mfr. #:: CD4031BPWR
描述:: Counter Shift Registers CMOS 64-St Static Shift Reg
生命週期:: 製造商新產品
數據表:: CD4031BPWR 數據表
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更多信息:: CD4031BPWR 更多信息 CD4031BPWR Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器移位寄存器

RoHS：: Y

計數順序：: 串行到串行

電路數量：: 1

位數：: 64 bit

包裝/案例：: TSSOP-16

邏輯系列：: CD4000

邏輯類型：: CMOS

輸入行數：: 2

傳播延遲時間：: 500 ns, 220 ns, 180 ns

電源電壓 - 最大值：: 18 V

最低工作溫度：: - 55 C

最高工作溫度：: + 125 C

打包：: 捲軸

功能：: 移位寄存器

工作溫度範圍：: - 55 C to + 125 C

系列：: CD4031B

寬度：: 4.4 mm

品牌：: 德州儀器

安裝方式：: 貼片/貼片

輸出線數：: 3

工作電源電壓：: 3.3 V, 5 V, 9 V, 12 V, 15 V

產品類別：: 計數器移位寄存器

出廠包裝數量：: 2000

子類別：: 邏輯 IC

單位重量：: 0.002183 oz

Tags: CD4031BPWR, CD4031BP, CD4031, CD403, CD40, CD4

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD4031BPWR 描述

***as Instruments: CMOS 64-Stage Static Shift Register 16-TSSOP -55 to 125

***ical: Shift Register Single 64-Bit Serial to Serial 16-Pin TSSOP T/R

***ark: Register Logic IC; No. of Elements:1; Output Type:Differential; Logic Case Style:TSSOP; No. of Pins:16; Supply Voltage Range:3V to 18V; Operating Temperature Range:-55°C to +125°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes

***AS INSTRUMENTS INCORPORATED: CD4031B is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage).

***AS INTRUMENTS: The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 12 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The CD4031B has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation. Alternatively, a delayed clock output (CLD) is provided that enables cascading register packages while allowing reduced clock drive fan-out and transition-time requirements. A third cascading option makes use of the Q' output from the 1/2 stage, which is available on the next negative-going transition of the clock after the Q output occurs. This delayed output, like the delayed clock CLD, is used with clocks having slow rise and fall times.

***AS INSTRUMENT: The CD4031B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4031BPWR 更多信息

Logic Solutions: OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More

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