CD74AC112M

CD74AC112M
Mfr. #:
CD74AC112M
描述:
Flip Flops Dual
生命週期:
製造商新產品
數據表:
CD74AC112M 數據表
交貨:
DHL FedEx Ups TNT EMS
支付:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
更多信息:
CD74AC112M 更多信息 CD74AC112M Product Details
產品屬性
屬性值
製造商:
德州儀器
產品分類:
人字拖
RoHS:
Y
電路數量:
2
邏輯系列:
交流電
邏輯類型:
JK 負沿觸發觸發器
極性:
反相/非反相
輸入類型:
CMOS、LVTTL
輸出類型:
微分
傳播延遲時間:
129 ns
高電平輸出電流:
- 24 mA
低電平輸出電流:
24 mA
電源電壓 - 最小值:
1.5 V
電源電壓 - 最大值:
5.5 V
最低工作溫度:
- 55 C
最高工作溫度:
+ 125 C
安裝方式:
貼片/貼片
包裝/案例:
SOP-16
打包:
管子
功能:
雙重的
高度:
1.58 mm
長度:
9.9 mm
工作溫度範圍:
- 55 C to + 125 C
靜態電流:
4 uA
系列:
CD74AC112
寬度:
3.91 mm
品牌:
德州儀器
通道數:
2
輸入行數:
2
輸出線數:
1
工作電源電壓:
1.5 V to 5.5 V
產品類別:
人字拖
重置類型:
設置、重置
出廠包裝數量:
40
子類別:
邏輯 IC
單位重量:
0.004998 oz
Tags
CD74AC112M, CD74AC11, CD74AC1, CD74AC, CD74A, CD74, CD7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    S***v
    S***v
    BG

    I'm very satisfied

    2019-06-19
    O***b
    O***b
    SA

    Very fast shipping

    2019-02-04
***as Instruments
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and eset 16-SOIC -55 to 125
***ical
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC Tube
***ark
LOGIC, DUAL JK FLIP-FLOP, 16SOIC
***i-Key
IC FF JK TYPE DUAL 1BIT 16SOIC
***AS INS
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
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可用性
庫存:
Available
訂購:
1984
輸入數量:
CD74AC112M的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
參考價格(美元)
數量
單價
小計金額
1
US$0.77
US$0.77
10
US$0.64
US$6.36
100
US$0.41
US$41.00
1000
US$0.33
US$328.00
2000
US$0.30
US$596.00
5000
US$0.28
US$1 385.00
10000
US$0.27
US$2 670.00
25000
US$0.26
US$6 425.00
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