SN74GTL16616DLG4

Mfr. #:: SN74GTL16616DLG4
描述:: Translation - Voltage Levels 17-Bit LVTTL-To-GTL/ GT=+ Univ Bus Trncvr
生命週期:: 製造商新產品
數據表:: SN74GTL16616DLG4 數據表
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更多信息:: SN74GTL16616DLG4 更多信息 SN74GTL16616DLG4 Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 轉換 - 電壓電平

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: SSOP-56

打包：: 管子

系列：: 74GTL

品牌：: 德州儀器

產品類別：: 轉換 - 電壓電平

出廠包裝數量：: 1

子類別：: 邏輯 IC

單位重量：: 0.024508 oz

Tags: SN74GTL16616DL, SN74GTL16616, SN74GTL1661, SN74GTL166, SN74GTL1, SN74G, SN74, SN7

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74GTL16616DLG4 描述

***i-Key: IC UNIV BUS TXRX 17BIT 56SSOP

***as Instruments: The SN74GTL16616 is a 17-bit UBT transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC circuitry. The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. V REF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB\ and CEBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB\ is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB\ also is low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CEBA\. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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