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TSB43AB21APDT

TSB43AB21APDT
Mfr. #:
TSB43AB21APDT
描述:
1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
生命週期:
製造商新產品
數據表:
TSB43AB21APDT 數據表
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更多信息:
TSB43AB21APDT 更多信息 TSB43AB21APDT Product Details
產品屬性
屬性值
製造商：
德州儀器
產品分類：
1394 Interface IC
RoHS：
Y
安裝方式：
貼片/貼片
包裝/案例：
TQFP-128
系列：
TSB43AB21A
產品：
IEEE 1394a
類型：
OHCI 山貓控制器
數據速率：
400 Mb/s
工作電源電壓：
3 V to 3.6 V
工作電源電流：
33 mA
最低工作溫度：
0 C
最高工作溫度：
+ 70 C
打包：
托盤
說明/功能：
OHCI 1.1, 1394A LINK LAYER CONTROLLER INTEGRATED WITH 1394A, 400MBPS, 1-PORT PHYSICAL LAYER (PHY)
品牌：
德州儀器
濕氣敏感：
是的
產品類別：
1394 Interface IC
支持的協議：
1394
出廠包裝數量：
90
子類別：
接口 IC
單位重量：
0.017760 oz
Tags
TSB43AB21APDT, TSB43AB21AP, TSB43AB21A, TSB43AB21, TSB43AB2, TSB43AB, TSB43A, TSB43, TSB4, TSB
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    M***i
    M***i
    RU

    Arrived the parcel in 13 days. The case when transporting was punctured. But it seems like everything is whole.

    2019-04-24
    I***.
    I***.
    ES

    Excelente

    2019-07-15
***Yang
Link Layer Controller Parallel/Serial Interface 3.3V 128-Pin TQFP Tray
***as Instruments
OHCI 1.1, 1394a link layer controller with integrated IEEE 1394a, 400-Mbps, 1-port PHY 128-TQFP 0 to 70
***SIT Distribution GmbH
Serial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
***el Electronic
Multilayer Ceramic Capacitors MLCC - SMD/SMT 50volts 6800pF C0G 5%
***ser
IEEE1394 (Firewire) OHCI 1.1, 1394a Link Layer Cntrlr Intgrt
***ark
PHY/LINK LAYER CONTROLLER, 400MBPS TQFP128
***ment14 APAC
1394 PHY/LINK LAYER CTRLR 128-TQFP
***DA Technology Co., Ltd.
Product Description Demo for Development.
***S
French Electronic Distributor since 1988
***et
IEEE 1394.A 400MBPS 1 PORT LINK-PHY
***i-Key Marketplace
TSB43AB21A OHCI 1.1, 1394A LINK
***nell
1394 PHY/LINK LAYER CTRLR 128-TQFP; Device Type:Link Layer Controller; Supply Voltage Range:3V to 3.6V; Driver Case Style:TQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; MSL:MSL 3 - 168 hours; SVHC:No SVHC (18-Jun-2012); Base Number:43; Interface Type:PCI; Package / Case:TQFP; Supply Voltage Max:3.6V; Supply Voltage Min:2.7V; Termination Type:SMD
***ical
Integrated 1394a-2000 OHCI PHY/Link-Layer Controller Serial Interface 3.3V 128-Pin TQFP Tray
***nell
IC, 1394A LINK LYR CNTLR 128-TQFP; Type de circuit: Contrôleur de couche liaison; Taux de transfert: 400Mbps; Tension, alimentation min.: 3V; Tension, alimentation max..: 3.6V; Type de boîtier CI Driver: TQFP; Nombre de broch
***ment14 APAC
IC, 1394A LINK LYR CNTLR 128-TQFP; Device Type:Link Layer Controller; Data Rate:400Mbps; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Driver Case Style:TQFP; No. of Pins:128Pins; Operating Temperature Min:0°C; Operating Temperature Max:70°C; Product Range:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (15-Jan-2019); Base Number:43; Operating Temperature Range:0°C to +70°C; Supply Current:92.4mA; Supply Voltage Range:3V to 3.6V; Termination Type:Surface Mount Device
***as Instruments
Enhanced Product Ieee 1394A-2000 Ohci Phy/Link Layer Controller 128-TQFP -40 to 85
*** Stop Electro
Serial I/O Controller, 3 Channel(s), 50MBps, CMOS, PQFP128
***ser
IEEE1394 (Firewire) Mil Enh OHCI PHY/ Link Layer Cntrlr
***ark
Controller IC; Supply Voltage Max:3.3V; Package/Case:128-TQFP; No. of Pins:128; Operating Temperature Range:-40°C to +85°C; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes ;RoHS Compliant: Yes
***ical
IEEE 1394a-2000 OHCI PHY/LINK Layer Controller Serial Interface 128-Pin TQFP Tray
***as Instruments
OHCI 1.1, 1394a link layer controller with integrated IEEE 1394a, 400-Mbps, 3-port PHY 128-TQFP 0 to 70
*** Stop Electro
Serial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
***ser
IEEE1394 (Firewire) OHCI 1.1, 1394a Link Layer Cntrlr Intgrt
***i-Key
IC IEEE-1394 CONTROLLER 128-TQFP
***DA Technology Co., Ltd.
Product Description Demo for Development.
***ource
original binding quality products
***i-Key Marketplace
TSB43AB23 OHCI 1.1, 1394A LINK L
***ark
Controller IC; Device Type:PHY/Link Layer Controller; Package/Case:128-TQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Data Rate:400Mbps ;RoHS Compliant: Yes
***as Instruments Inc.
The Texas Instruments TSB43AB21A device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB21A device provides one 1394 port. The TSB43AB21A device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
***as Instruments Inc.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB21A device is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The TSB43AB21A device supports the D0, D1, D2, and D3 power states.
***AS INS
The TSB43AB21A design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data.
***AS INTRUMENTS
The TSB43AB21A device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB43AB21A device also provides multiple isochronous contexts, multiple cacheline burst transfers, and advanced internal arbitration.
***
An advanced CMOS process achieves low power consumption and allows the TSB43AB21A device to operate at PCI clock rates up to 33 MHz.
***TEXAS
The TSB43AB21A PHY-layer provides the digital and analog transceiver functions needed to implement a single-port node in a cable-based 1394 network. The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
***AS INSTRUMENTS INCORPORATED
The TSB43AB21A PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data.
***INS
Data bits to be transmitted through the cable port are received from the integrated LLC and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair, and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair.
***AS INSTRUMENTS INC
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are resynchronized to the local 49.152-MHz system clock and sent to the integrated LLC.
***ASI
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.
***ASI
The TSB43AB21A device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1.0 µF.
***OMO Electronic
The line drivers in the TSB43AB21A device operate in a high-impedance current mode and are designed to work with external 112- ±1%.
***OMO Electronic
When the power supply of the TSB43AB21A device is off and the twisted-pair cables are connected, the TSB43AB21A transmitter and receiver circuitry present a high impedance to the cable and do not load the TPBIAS voltage at the other end of the cable.
***AS INSTRUM
When the device is in a low-power state (for example, D2 or D3) the TSB43AB21A device automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB43AB21A device disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected or disabled with the port interrupt enable bit cleared.
***TEXAS
The TSB43AB21A device exits the low-power mode when bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 or when a port event occurs which requires that the TSB43AB21A device to become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is detected on a nondisabled port). When the TSB43AB21A device is in the low-power mode, the internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.
***AS INSTRUMENTS INCORPORATED
The TSB43AB21A device supports hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The enhancements include automatic timestamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.
***AS
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP formats. The TSB43AB21A device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale—that is, the value is less than the current cycle timer when the packet is transmitted.
型號 描述 庫存 價格
TSB43AB21APDT
DISTI # 296-12698-ND		IC PHY/LINK LAYER CTRLR 128-TQFP
RoHS: Compliant
Min Qty: 90
Container: Tray		Temporarily Out of Stock
  • 90:$9.2332
TSB43AB21APDTG4
DISTI # TSB43AB21APDTG4-ND		IC PHY/LINK LAYER CTRLR 128-TQFP
RoHS: Compliant
Min Qty: 90
Container: Tube		Temporarily Out of Stock
  • 90:$9.2332
TSB43AB21APDT
DISTI # TSB43AB21APDT		OHCI PHY/Link Layer Controller 128-Pin TQFP Tray - Trays (Alt: TSB43AB21APDT)
RoHS: Compliant
Min Qty: 90
Container: Tray		Americas - 0
  • 90:$8.9900
  • 180:$8.9900
  • 360:$8.9900
  • 540:$8.8900
  • 900:$8.8900
TSB43AB21APDT
DISTI # TSB43AB21APDT		OHCI PHY/Link Layer Controller 128-Pin TQFP Tray (Alt: TSB43AB21APDT)
RoHS: Compliant
Min Qty: 1
Container: Tray		Europe - 0
  • 1:€7.4900
  • 10:€6.9900
  • 25:€6.5900
  • 50:€6.2900
  • 100:€5.8900
  • 500:€5.5900
  • 1000:€5.3900
TSB43AB21APDTG4
DISTI # TSB43AB21APDTG4		OHCI PHY/Link Layer Controller 128-Pin TQFP Tray (Alt: TSB43AB21APDTG4)
RoHS: Compliant
Min Qty: 1
Container: Tray		Europe - 0
  • 1:€7.4900
  • 10:€6.9900
  • 25:€6.5900
  • 50:€6.2900
  • 100:€5.8900
  • 500:€5.5900
  • 1000:€5.3900
TSB43AB21APDTG4
DISTI # TSB43AB21APDTG4		OHCI PHY/Link Layer Controller 128-Pin TQFP Tray - Rail/Tube (Alt: TSB43AB21APDTG4)
RoHS: Compliant
Min Qty: 90
Container: Tube		Americas - 0
  • 90:$6.4900
  • 180:$6.1900
  • 360:$5.9900
  • 540:$5.7900
  • 900:$5.5900
TSB43AB21APDT
DISTI # 595-TSB43AB21APDT		1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
RoHS: Compliant		0
  • 1:$10.7200
  • 10:$9.6900
  • 25:$8.9700
  • 100:$8.0200
  • 250:$7.6200
  • 500:$6.9900
  • 1000:$6.0900
TSB43AB21APDTG4
DISTI # 595-TSB43AB21APDTG4		1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
RoHS: Compliant		0
  • 90:$8.9700
  • 180:$8.0200
  • 270:$7.6200
  • 540:$6.9900
  • 1080:$6.0900
TSB43AB21APDTSerial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
RoHS: Compliant		34299
  • 1000:$5.9200
  • 500:$6.2300
  • 100:$6.4900
  • 25:$6.7700
  • 1:$7.2900
TSB43AB21APDTG4Serial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
RoHS: Compliant		15
  • 1000:$5.9200
  • 500:$6.2300
  • 100:$6.4900
  • 25:$6.7700
  • 1:$7.2900
TSB43AB21APDTBUS Controller Circuit, 128 Pin, TQFP92
  • 33:$7.3075
  • 10:$7.9000
  • 1:$11.8500
TSB43AB21APDTSerial I/O Controller, 1 Channel(s), 50MBps, CMOS, PQFP128
RoHS: Not Compliant		Europe - 172
    TSB43AB21APDT
    DISTI # C1S746200565092    		OHCI PHY/Link Layer Controller 128-Pin TQFP Tray
    RoHS: Compliant    		31
    • 25:$8.0990
    • 10:$8.6969
    • 1:$9.4850
    圖片 型號 描述
    TSB43AB21AIPDTEP

    Mfr.#: TSB43AB21AIPDTEP

    OMO.#: OMO-TSB43AB21AIPDTEP

    		 1394 Interface IC Mil Enh Int OCHI pHY Link-Layer Cntrlr
    TSB43AB22APDT

    Mfr.#: TSB43AB22APDT

    OMO.#: OMO-TSB43AB22APDT

    		 1394 Interface IC OHCI 1.1 1394a Link Layer Cntrlr Intgrt
    TSB43AB22APDTG4

    Mfr.#: TSB43AB22APDTG4

    OMO.#: OMO-TSB43AB22APDTG4-TEXAS-INSTRUMENTS

    		 IC CONTROLLER LINK LAYER 128TQFP
    TSB43AA82A

    Mfr.#: TSB43AA82A

    OMO.#: OMO-TSB43AA82A-1190

    		 全新原裝
    TSB43AA82GGW

    Mfr.#: TSB43AA82GGW

    OMO.#: OMO-TSB43AA82GGW-TEXAS-INSTRUMENTS

    		 IC LINK LAYER CONTROLLER 176-BGA
    TSB43AB23

    Mfr.#: TSB43AB23

    OMO.#: OMO-TSB43AB23-1190

    		 全新原裝
    TSB43AB23PFT

    Mfr.#: TSB43AB23PFT

    OMO.#: OMO-TSB43AB23PFT-1190

    		 全新原裝
    TSB43AB82

    Mfr.#: TSB43AB82

    OMO.#: OMO-TSB43AB82-1190

    		 全新原裝
    TSB43AC42PGFG4

    Mfr.#: TSB43AC42PGFG4

    OMO.#: OMO-TSB43AC42PGFG4-1190

    		 全新原裝
    TSB43AA82APGEG4

    Mfr.#: TSB43AA82APGEG4

    OMO.#: OMO-TSB43AA82APGEG4-TEXAS-INSTRUMENTS

    		 IC PHY LINK LAYR HP 2PRT 144LQFP
    可用性
    庫存:
    Available
    訂購:
    5500
    輸入數量:
    TSB43AB21APDT的當前價格僅供參考，如果您想獲得最優惠的價格，請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
    參考價格（美元）
    數量
    單價
    小計金額
    90
    US$8.97
    US$807.30
    180
    US$8.02
    US$1 443.60
    270
    US$7.62
    US$2 057.40
    540
    US$6.99
    US$3 774.60
    1080
    US$6.09
    US$6 577.20
    由於2021年半導體供不應求，低於2021年之前的正常價格，請發詢價確認。
    從...開始
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