SN74ACT7805-20DLR

Mfr. #:: SN74ACT7805-20DLR
描述:: IC CLOCKED FIFO 256X18 56-SSOP
生命週期:: 製造商新產品
數據表:: SN74ACT7805-20DLR 數據表
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更多信息:: SN74ACT7805-20DLR 更多信息 SN74ACT7805-20DLR Product Details

產品屬性
屬性值

製造商: 德州儀器

產品分類: 邏輯 - FIFO 存儲器

系列: 74ACT

打包: 捲帶 (TR)

包裝盒: 56-BSSOP (0.295", 7.50mm Width)

工作溫度: 0°C ~ 70°C

安裝型: 表面貼裝

功能: 同步

電壓供應: 4.5 V ~ 5.5 V

供應商-設備-包: 56-SSOP

內存大小: 4.5K (256 x 18)

數據速率: 50MHz

訪問時間: 13ns

最大電流供應: 400μA

巴士定向: 單向

擴展型: 寬度

可編程標誌支持: 是的

轉發能力: 不

FWFT-支持: 不

Tags: SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT7805-20DLR 評級和評論

H***n

nice

2019-05-26

F***m

2019-04-08

SN74ACT7805-20DLR 描述

***et: FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R

***i-Key: IC CLOCKED FIFO 256X18 56-SSOP

***as Instruments: The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.

Market price

型號	描述	庫存	價格
SN74ACT7805-20DLR DISTI # SN74ACT7805-20DLR-ND	IC CLOCKED FIFO 256X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ACT7805-20DLR DISTI # 595-SN74ACT780520DLR	FIFO 256 x 18 synchronous FIFO memory RoHS: Compliant	0
SN74ACT7805-20DLR	FIFO, 256X18, 13ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	36750	1000:$15.7100 500:$16.5400 100:$17.2200 25:$17.9600 1:$19.3400

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