SN74F163ADBRE4

Mfr. #:: SN74F163ADBRE4
描述:: Counter ICs Synchronous 4-Bit Binary Counter
生命週期:: 製造商新產品
數據表:: SN74F163ADBRE4 數據表
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更多信息:: SN74F163ADBRE4 更多信息 SN74F163ADBRE4 Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器 IC

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: SSOP-16

計數器類型：: 二進制

邏輯系列：: TTL

位數：: 4

計數方法：: 同步

工作電源電壓：: 4.5 V to 5.5 V

最低工作溫度：: 0 C

最高工作溫度：: + 70 C

打包：: 捲軸

工作溫度範圍：: 0 C to + 70 C

品牌：: 德州儀器

產品類別：: 計數器 IC

出廠包裝數量：: 1

子類別：: 計數器 IC

單位重量：: 0.004536 oz

Tags: SN74F163ADBR, SN74F163ADB, SN74F163AD, SN74F163, SN74F16, SN74F1, SN74F, SN74, SN7

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We provide 90-360 days warranty.

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74F163ADBRE4 描述

***ser: Logic - Counters Synchronous 4-Bit Binary Counter

***ark: Counter Logic IC; Logic Family:F; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:16-SSOP; No. of Pins:16; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes; Output Type:TTL ;RoHS Compliant: Yes

***as Instruments: This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK. This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT. The clear function is synchronous, and a low logic level at the clear (CLR\) input sets all four of the flip-flop outputs to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.

Market price

型號	描述	庫存
SN74F163ADBRE4 DISTI # SN74F163ADBRE4-ND	IC COUNTER 4BIT BIN SYNC 16-SSOP RoHS: Compliant Min Qty: 2000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74F163ADBRE4 DISTI # SN74F163ADBRE4	- Bulk (Alt: SN74F163ADBRE4) Min Qty: 1 Container: Bulk	Americas - 0
SN74F163ADBRE4 DISTI # 595-SN74F163ADBRE4	Counter ICs Synchronous 4-Bit Binary Counter RoHS: Compliant	0

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