SN74LVT8980ADWR

Mfr. #:: SN74LVT8980ADWR
描述:: Specialty Function Logic Emb Test-Bus Cntrl w/8-Bit Id Buses
生命週期:: 製造商新產品
數據表:: SN74LVT8980ADWR 數據表
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更多信息:: SN74LVT8980ADWR 更多信息 SN74LVT8980ADWR Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 專業功能邏輯

RoHS：: Y

產品：: 邊界掃描 JTAG 邏輯

系列：: SN74LVT8980A

工作電源電壓：: 2.7 V to 3.6 V

最低工作溫度：: - 40 C

最高工作溫度：: + 85 C

包裝/案例：: SOIC-24

打包：: 捲軸

工作溫度範圍：: - 40 C to + 85 C

品牌：: 德州儀器

安裝方式：: 貼片/貼片

產品類別：: 專業功能邏輯

出廠包裝數量：: 2000

子類別：: 邏輯 IC

單位重量：: 0.022025 oz

Tags: SN74LVT8980AD, SN74LVT8980A, SN74LVT8980, SN74LVT898, SN74LVT8, SN74LVT, SN74LV, SN74L, SN74, SN7

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74LVT8980ADWR 評級和評論

T***s

works

2019-04-17

T***l

nothing against

2019-04-06

V***v

Parcel received, quickly, everything corresponds

2019-03-09

E**c

I ordered from this seller for the first time. I was very pleased with the order. Prompt shipment of goods and fast delivery. Everything is very well done, and meets the characteristics of the stated suppliers. in the future I plan to continue to order from this seller. I recommend it to everyone.

2019-05-26

SN74LVT8980ADWR 描述

***ark: 8 BIT GENERIC HOST INTERFACE, SOIC-24, FULL REEL

***as Instruments: Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces 24-SOIC -40 to 85

***ical: Embedded Test Bus Controller 3.3V 24-Pin SOIC T/R

***ASIN: The LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.

***AS INSTRUMENTS INC: The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST)\. All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBCs automatically handle all associated serial-data justification.

***AS INSTRUMEN: Conceptually, the eTBCs operate as simple 8-bit memory- or I/O-mapped peripherals to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBCs via their generic host interface, which includes an 8-bit data bus (D7D0) and a 3-bit address bus (A2A0). Read/write select (R/W\) and strobe (STRB)\ signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBCs cannot respond immediately to the requested read/write operation.

***AS: High-level commands are issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles.

***AS INSRUMENT: During scan operations, serial data that appears at the TDI input is transferred into a serial to 4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel to serial FIFO write buffer.

***as Instruments (TI): In addition to such simple state-movement, scan, and run-test operations, the eTBCs support several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TIs addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBCs.

***AS INTRUMENTS: The eTBCs flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode also is available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by the eTBCs, even where such may not fully comply to IEEE Std 1149.1

***as Instr.: While most operations of the eTBCs are synchronous to CLKIN, a test-output enable (TOE)\ is provided for output control of the TAP outputs, and a reset (RST)\ input is provided for hardware reset of the eTBCs. The former can be used to disable the eTBCs so that an external controller can master the associated IEEE Std 1149.1 test bus.

SN74LVT8980ADWR 更多信息

Logic Solutions: OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More

Market price

型號	描述	庫存	價格
SN74LVT8980ADWR DISTI # 296-15986-2-ND	IC TEST-BUS CONTROLLER 24-SOIC RoHS: Compliant Min Qty: 2000 Container: Tape & Reel (TR)	Temporarily Out of Stock	2000:$7.4470
SN74LVT8980ADWRG4 DISTI # SN74LVT8980ADWRG4-ND	IC TEST-BUS CONTROLLER 24-SOIC RoHS: Compliant Min Qty: 2000 Container: Tape & Reel (TR)	Temporarily Out of Stock	2000:$7.4470
SN74LVT8980ADWR DISTI # SN74LVT8980ADWR	Embedded Test Bus Controller 24-Pin SOIC T/R - Tape and Reel (Alt: SN74LVT8980ADWR) RoHS: Compliant Min Qty: 2000 Container: Reel	Americas - 0	2000:$8.3900 4000:$7.9900 8000:$7.6900 12000:$7.4900 20000:$7.1900
SN74LVT8980ADWR DISTI # SN74LVT8980ADWR	Embedded Test Bus Controller 24-Pin SOIC T/R (Alt: SN74LVT8980ADWR) RoHS: Compliant Min Qty: 2000 Container: Tape and Reel	Europe - 0	2000:€9.1900 4000:€8.2900 8000:€7.5900 12000:€7.2900 20000:€6.9900
SN74LVT8980ADWRG4 DISTI # SN74LVT8980ADWRG4	Embedded Test Bus Controller 24-Pin SOIC T/R - Tape and Reel (Alt: SN74LVT8980ADWRG4) RoHS: Compliant Min Qty: 2000 Container: Reel	Americas - 0	2000:$8.3900 4000:$7.9900 8000:$7.6900 12000:$7.4900 20000:$7.1900
SN74LVT8980ADW DISTI # 595-SN74LVT8980ADW	Specialty Function Logic Emb Test-Bus Cntrl w/8-Bit Id Buses RoHS: Compliant	21	1:$15.7000 10:$14.4400 25:$13.6900 100:$12.2000 250:$11.6000 500:$10.8500
SN74LVT8980ADWR DISTI # 595-SN74LVT8980ADWR	Specialty Function Logic Emb Test-Bus Cntrl w/8-Bit Id Buses RoHS: Compliant	0	1:$12.2100 10:$11.2300 25:$10.6500 100:$9.4900 250:$9.0200 500:$8.4400 1000:$7.7400
SN74LVT8980ADWRG4 DISTI # 595-SN74LVT8980ADWG4	Specialty Function Logic Emb Test-Bus Cntrl w/8-Bit Id Buses RoHS: Compliant	0	2000:$7.7400
SN74LVT8980ADWR	Microprocessor Circuit, CMOS, PDSO24 RoHS: Compliant	3451	1000:$8.5600 500:$9.0100 100:$9.3800 25:$9.7800 1:$10.5300
SN74LVT8980ADWRG4	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO24 (Also Known As: SN74LVT8980ADWR)	589	575:$4.9875 352:$5.2250 1:$14.2500
SN74LVT8980ADWRG4	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO24	589	575:$4.9875 352:$5.2250 1:$14.2500
SN74LVT8980ADWRG4		52

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