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74SSTUB32868AZRHR

74SSTUB32868AZRHR
Mfr. #:
74SSTUB32868AZRHR
描述:
Registers 28-56B Registered Buffer
生命週期:
製造商新產品
數據表:
74SSTUB32868AZRHR 數據表
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74SSTUB32868AZRHR 更多信息 74SSTUB32868AZRHR Product Details
產品屬性
屬性值
製造商：
德州儀器
產品分類：
寄存器
RoHS：
Y
邏輯類型：
CMOS
邏輯系列：
上海交通大學
電路數量：
1
最大時鐘頻率：
410 MHz
傳播延遲時間：
1 ns
高電平輸出電流：
- 8 mA
低電平輸出電流：
8 mA
電源電壓 - 最大值：
1.9 V
電源電壓 - 最小值：
1.7 V
最低工作溫度：
- 40 C
最高工作溫度：
+ 85 C
包裝/案例：
nFBGA-176
打包：
捲軸
高度：
1.5 mm
輸入類型：
單端
長度：
15 mm
系列：
74SSTUB32868A
寬度：
6 mm
品牌：
德州儀器
安裝方式：
貼片/貼片
通道數：
28
輸入行數：
28
輸出線數：
56
濕氣敏感：
是的
工作電源電壓：
1.8 V
極性：
反相/非反相
產品類別：
寄存器
重置類型：
異步
出廠包裝數量：
1000
子類別：
邏輯 IC
觸發類型：
上升沿/下降沿
單位重量：
0.010935 oz
Tags
74SSTUB32868, 74SSTUB3, 74SSTUB, 74SSTU, 74SS, 74S
Service Guarantees

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA -40 to 85
***ical
Registered Buffer Single-Element 28-CH CMOS 176-Pin NFBGA T/R
***ark
Logic - Clock Generator IC; No. of Outputs:56; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Package/Case:176-BGA; No. of Pins:176; Operating Temperature Range:-40°C to +85°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***AS INSTRU
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 stacked SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads.
***XS
All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.
***AS
The 74SSTUB32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
***AS INSTRUMENT
The 74SSTUB32868A accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.
***AS INSTRUMENT
The 74SSTUB32868A includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered, the corresponding QERR signal is generated.
***AS INTRUMENTS
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before the device enters the low-power mode (LPM) and the QERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity check computation.
***as Instruments (TI)
The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low or high level to configure the register in the desired mode.
***NS
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32868A must ensure that the outputs remain low, thus ensuring no glitches on the output.
***INS
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
***NS
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C inputs always must be held at a valid logic high or low level.
***INS
The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1 is low, the QERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control and when driven low forces the Qn outputs low, and the QERR output high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0 and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only, then the CSGEN input should be pulled up to VCC through a pullup resistor.
***OMO Electronic
The two VREF pins (A5 and AB5) are connected together internally by approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
型號 描述 庫存 價格
74SSTUB32868AZRHR
DISTI # 296-22020-1-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 1
Container: Cut Tape (CT)		356In Stock
  • 500:$11.4507
  • 100:$12.8721
  • 10:$15.2410
  • 1:$16.5800
74SSTUB32868AZRHR
DISTI # 296-22020-6-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 1
Container: Digi-Reel®		356In Stock
  • 500:$11.4507
  • 100:$12.8721
  • 10:$15.2410
  • 1:$16.5800
74SSTUB32868AZRHR
DISTI # 296-22020-2-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Temporarily Out of Stock
  • 1000:$10.1971
74SSTUB32868AZRHR
DISTI # 74SSTUB32868AZRHR		Registered Buffer Single 28-CH CMOS 176-Pin NFBGA T/R - Tape and Reel (Alt: 74SSTUB32868AZRHR)
RoHS: Compliant
Min Qty: 1000
Container: Reel		Americas - 0
  • 1000:$11.0900
  • 2000:$10.4900
  • 4000:$10.1900
  • 6000:$9.7900
  • 10000:$9.5900
74SSTUB32868AZRHR
DISTI # 74SSTUB32868AZRHR		Registered Buffer Single 28-CH CMOS 176-Pin NFBGA T/R (Alt: 74SSTUB32868AZRHR)
RoHS: Compliant
Min Qty: 1000
Container: Tape and Reel		Europe - 0
  • 1000:€12.0900
  • 2000:€10.9900
  • 4000:€9.9900
  • 6000:€9.5900
  • 10000:€9.1900
74SSTUB32868AZRHR28-Bit to 56-Bit Registered Buffer with Address-Parity Test3000
  • 1000:$8.7100
  • 750:$8.7400
  • 500:$9.7400
  • 250:$10.5800
  • 100:$11.1200
  • 25:$12.7300
  • 10:$13.1900
  • 1:$14.1800
74SSTUB32868AZRHRD Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA176
RoHS: Compliant		16252
  • 1000:$10.0900
  • 500:$10.6200
  • 100:$11.0600
  • 25:$11.5300
  • 1:$12.4200
74SSTUB32868AZRHR
DISTI # 595-SSTUB32868AZRHR		Registers 28-56B Registered Buffer
RoHS: Compliant		0
  • 1:$16.1000
  • 10:$14.8000
  • 25:$14.0300
  • 100:$12.5000
  • 250:$11.8900
  • 500:$11.1200
  • 1000:$10.2000
圖片 型號 描述
74SSTUB32868AZRHR

Mfr.#: 74SSTUB32868AZRHR

OMO.#: OMO-74SSTUB32868AZRHR

 Registers 28-56B Registered Buffer
74SSTUB32866AZKER

Mfr.#: 74SSTUB32866AZKER

OMO.#: OMO-74SSTUB32866AZKER

 Registers 25B Config Registerd Buffer
74SSTUB32864AZKER

Mfr.#: 74SSTUB32864AZKER

OMO.#: OMO-74SSTUB32864AZKER

 Registers 25-Bit Configurable Registered Buffer
74SSTUB32865AZJBR

Mfr.#: 74SSTUB32865AZJBR

OMO.#: OMO-74SSTUB32865AZJBR

 Registers 28B-56B Reg Buffer
74SSTUB32866BBFG

Mfr.#: 74SSTUB32866BBFG

OMO.#: OMO-74SSTUB32866BBFG-1190

 全新原裝
74SSTUB32868ZRHR BGA

Mfr.#: 74SSTUB32868ZRHR BGA

OMO.#: OMO-74SSTUB32868ZRHR-BGA-1190

 全新原裝
74SSTUB32868AZRHR

Mfr.#: 74SSTUB32868AZRHR

OMO.#: OMO-74SSTUB32868AZRHR-TEXAS-INSTRUMENTS

 Registers 28-56B Registered Buffe
74SSTUB32865ZJBR

Mfr.#: 74SSTUB32865ZJBR

OMO.#: OMO-74SSTUB32865ZJBR-TEXAS-INSTRUMENTS

 Registers 28B-56B Reg Buffe
74SSTUB32868ZRHR

Mfr.#: 74SSTUB32868ZRHR

OMO.#: OMO-74SSTUB32868ZRHR-TEXAS-INSTRUMENTS

 Registers 28B-56B Reg Buffe
74SSTUB32864AZKER

Mfr.#: 74SSTUB32864AZKER

OMO.#: OMO-74SSTUB32864AZKER-TEXAS-INSTRUMENTS

 Registers 25-Bit Configurable Registered Buffe
可用性
庫存:
Available
訂購:
5000
輸入數量:
74SSTUB32868AZRHR的當前價格僅供參考，如果您想獲得最優惠的價格，請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
參考價格（美元）
數量
單價
小計金額
1
US$16.10
US$16.10
10
US$14.80
US$148.00
25
US$14.03
US$350.75
100
US$12.50
US$1 250.00
250
US$11.89
US$2 972.50
500
US$11.12
US$5 560.00
由於2021年半導體供不應求，低於2021年之前的正常價格，請發詢價確認。
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