CY14V101QS-BK108XI

Mfr. #:: CY14V101QS-BK108XI
製造商:: Cypress Semiconductor
描述:: NVRAM 1-Mbit (128KX8) Quad SPI nvSRAM
生命週期:: 製造商新產品
數據表:: CY14V101QS-BK108XI 數據表
交貨:: DHL FedEx Ups TNT EMS
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ECAD Model:
更多信息:: CY14V101QS-BK108XI 更多信息 CY14V101QS-BK108XI Product Details

產品屬性
屬性值

製造商：: 賽普拉斯半導體

產品分類：: NVRAM

RoHS：: Y

包裝/案例：: FBGA-24

接口類型：: SPI

內存大小：: 1 Mbit

組織：: 128 k x 8

數據總線寬度：: 8 bit

電源電壓 - 最大值：: 3.6 V

電源電壓 - 最小值：: 2.7 V

工作電源電流：: 33 mA

最低工作溫度：: - 40 C

最高工作溫度：: + 85 C

系列：: CY14V101

打包：: 托盤

品牌：: 賽普拉斯半導體

安裝方式：: 貼片/貼片

濕氣敏感：: 是的

Pd - 功耗：: 1 W

產品類別：: NVRAM

出廠包裝數量：: 480

子類別：: 內存和數據存儲

單位重量：: 0.021164 oz

Tags: CY14V101QS-B, CY14V101QS, CY14V101Q, CY14V101, CY14V10, CY14V1, CY14V, CY14, CY1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CY14V101QS-BK108XI 描述

***ical: NVRAM NVSRAM Serial-SPI 1Mbit 3V 24-Pin FBGA Tray

***et: 1MB NVSRAM WITH A QUAD SERIAL PERIPHERAL INTERFACE

***i-Key: IC NVSRAM 1M SPI 108MHZ 24FBGA

CY14V101QS-BK108XI 更多信息

CY14V101 1-Mb Quad SPI nvSRAM: Cypress Semiconductor CY14V101 1-Mbit (128K × 8) Quad SPI nvSRAM couples a 1-Mbit nvSRAM with a QPI interface. The QPI enables writing and reading of the memory in either a single (one I/O channel for one bit per clock cycle), dual (two I/O channels for two bits per clock cycle), or quad (four I/O channels for four bits per clock cycle) through the use of specific opcodes. The memory is organized as 128Kbytes each consisting of SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide storage of data. Data transfers from SRAM to the nonvolatile cells (STORE operation) occur automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile cells (RECALL operation). Users may also initiate the STORE and RECALL operations through SPI instructions.Learn More

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