DC1884A-F

Mfr. #:: DC1884A-F
製造商:: Analog Devices Inc.
描述:: Data Conversion IC Development Tools LTM9006-14 - 14-Bit, 25Msps, 1.8V Octal
生命週期:: 製造商新產品
數據表:: DC1884A-F 數據表
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更多信息:: DC1884A-F 更多信息 DC1884A-F Product Details

產品屬性
屬性值

製造商：: 模擬設備公司

產品分類：: 數據轉換IC開發工具

RoHS：: Y

產品：: 演示板

類型：: 模數轉換器

工具用於評估：: LTM9006-14

工作電源電壓：: 3.3 V to 6 V

系列：: LTM9006

品牌：: 模擬設備公司

產品類別：: 數據轉換IC開發工具

出廠包裝數量：: 1

子類別：: 開發工具

Tags: DC188, DC18, DC1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

DC1884A-F 描述

***va Crawler: LTM9006-14 | 14-Bit, 25Msps, 1.8V Octal Serial ADC, 1MHz < Ain < 70MHz, req DC1371 and DC1075

***ark: Evaluation Board, Adc; Silicon Manufacturer:linear Technology; Silicon Core Number:ltm9006-14; No. Of Bits:14Bit; Sample Rate:25Msps; Kit Application Type:data Converter; Application Sub Type:adc; Product Range:- Rohs Compliant: Na

***log Devices: The LTM9008-14/LTM9007-14/LTM9006-14 are 8-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73dB SNR and 90dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flowthrough pinout reduces overall board space requirements. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Applications Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing

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