CD40193BPWR

Mfr. #:: CD40193BPWR
描述:: Counter ICs Presettable UpDn BCD
生命週期:: 製造商新產品
數據表:: CD40193BPWR 數據表
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更多信息:: CD40193BPWR 更多信息 CD40193BPWR Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器 IC

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: TSSOP-16

計數器類型：: 二進制

邏輯系列：: CD4000

位數：: 4 bit

計數方法：: 同步

計數順序：: 上/下

工作電源電壓：: 3 V to 18 V

最低工作溫度：: - 55 C

最高工作溫度：: + 125 C

系列：: CD40193B

打包：: 捲軸

功能：: 櫃檯

輸入電壓：: - 0.5 V to + 0.5 V

工作溫度範圍：: - 55 C to + 125 C

輸出電流：: +/- 1.5 mA

輸出電壓：: 3.0 V to 18 V

品牌：: 德州儀器

Pd - 功耗：: 500 mW (1/2 W)

產品類別：: 計數器 IC

出廠包裝數量：: 2000

子類別：: 計數器 IC

單位重量：: 0.002183 oz

Tags: CD40193BP, CD40193B, CD40193, CD4019, CD401, CD40, CD4

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD40193BPWR 評級和評論

M***v

The goods went very long, tracked badly!

2019-05-21

V***v

Normal in appearance. There is a lubricated marking. I did not experience in work.

2019-03-11

CD40193BPWR 描述

***as Instruments: CMOS Presettable Binary Up/Down Counter (Dual Clock with Reset) 16-TSSOP -55 to 125

***ical: Counter Single 4-Bit Async Binary UP/Down 16-Pin TSSOP T/R

***ark: BINARY UP/DOWN COUNTER, CMOS TSSOP16, FULL REEL

***i-Key: IC UP/DOWN COUNTR BINARY 16TSSOP

***ser: Logic - Counters Presettable UpDn BCD

***i-Key Marketplace: CD40193B CMOS PRESETTABLE BINARY

***INS: CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided.

***AS INSTRUMENTS INCORPORATED: The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low.

***AS INSRUMENT: The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.

***AS INST: The CARRY\ and BORROW\ signals are high with the counter is counting up or down. The CARRY\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\ and CARRY\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.

***TEXAS: The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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