CD4026BNSR

Mfr. #:: CD4026BNSR
描述:: Counter ICs CMOS Decade Counter/ Divider
生命週期:: 製造商新產品
數據表:: CD4026BNSR 數據表
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產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 計數器 IC

RoHS：: Y

安裝方式：: 貼片/貼片

包裝/案例：: SO-16

計數器類型：: 十年

邏輯系列：: CD4000

位數：: 7 bit

工作電源電壓：: 3 V to 18 V

最低工作溫度：: - 55 C

最高工作溫度：: + 125 C

系列：: CD4026B

打包：: 捲軸

功能：: 櫃檯

工作溫度範圍：: - 55 C to + 125 C

輸出電流：: +/- 1.5 mA

品牌：: 德州儀器

產品類別：: 計數器 IC

出廠包裝數量：: 2000

子類別：: 計數器 IC

單位重量：: 0.007079 oz

Tags: CD4026BN, CD4026, CD402, CD40, CD4

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD4026BNSR 描述

***as Instruments: CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable 16-SO -55 to 125

***ical: Counter/Divider Single 5-Bit Decade UP 16-Pin SOP T/R

***ser: Logic - Counters CMOS Decade Counter/ Divider

***i-Key: IC COUNTER/DIVIDER DECADE 16SO

***ark: Counter Logic IC; Counter Type:Decade Counter / Divider; Clock Speed:16MHz; Supply Voltage Range:3V to 18V; Logic Case Style:SOIC; No. of Pins:16; Operating Temperature Range:-55°C to +125°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes

***AS INTRUMENTS: CD4026B and CD4033B each consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display.

***AS INSRUMENTS: These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important.

***XS: Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. Signals peculiar to the CD4033B are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT.

***XS: A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the CD4033B; in the CD4026B these outputs go high only when the DISPLAY ENABLE IN is high.

***as Instruments (TI): The CD4026B- and CD4033B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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