AD60003RSZ24RL7

AD60003RSZ24RL7
Mfr. #:
AD60003RSZ24RL7
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AD60003RSZ24RL7 數據表
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Tags
AD60003, AD6000, AD600, AD60, AD6
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***log Devices
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD807 consumes 140 mW and operates from a single power supply at either +5 V or –5.2 V.
型號 製造商 描述 庫存 價格
AD60003RS24XRL7ad 
RoHS: Not Compliant
Europe - 3223
    圖片 型號 描述
    AD60003

    Mfr.#: AD60003

    OMO.#: OMO-AD60003-1190

    全新原裝
    AD60003RS24XRL7

    Mfr.#: AD60003RS24XRL7

    OMO.#: OMO-AD60003RS24XRL7-1190

    全新原裝
    AD60003RSZ24RL7

    Mfr.#: AD60003RSZ24RL7

    OMO.#: OMO-AD60003RSZ24RL7-1190

    全新原裝
    AD60003X

    Mfr.#: AD60003X

    OMO.#: OMO-AD60003X-1190

    全新原裝
    AD60003XGA1313.1

    Mfr.#: AD60003XGA1313.1

    OMO.#: OMO-AD60003XGA1313-1-1190

    全新原裝
    可用性
    庫存:
    Available
    訂購:
    2000
    輸入數量:
    AD60003RSZ24RL7的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
    參考價格(美元)
    數量
    單價
    小計金額
    1
    US$0.00
    US$0.00
    10
    US$0.00
    US$0.00
    100
    US$0.00
    US$0.00
    500
    US$0.00
    US$0.00
    1000
    US$0.00
    US$0.00
    由於2021年半導體供不應求,低於2021年之前的正常價格,請發詢價確認。
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