SN74V215-10PAG

Mfr. #:: SN74V215-10PAG
描述:: FIFO 512 x 18 Synchronous FIFO Memory
生命週期:: 製造商新產品
數據表:: SN74V215-10PAG 數據表
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更多信息:: SN74V215-10PAG 更多信息 SN74V215-10PAG Product Details

產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 先進先出

RoHS：: Y

數據總線寬度：: 18 bit

巴士方向：: 單向

內存大小：: 9 kbit

計時類型：: 同步

組織：: 512 x 18

電路數量：: 2

最大時鐘頻率：: 100 MHz

訪問時間：: 6.5 ns

電源電壓 - 最大值：: 3.6 V

電源電壓 - 最小值：: 3 V

電源電流 - 最大值：: 35 mA

最低工作溫度：: 0 C

最高工作溫度：: + 70 C

包裝/案例：: TQFP-64

打包：: 托盤

高度：: 1 mm

系列：: SN74V215

寬度：: 10 mm

品牌：: 德州儀器

安裝方式：: 貼片/貼片

濕氣敏感：: 是的

工作電源電壓：: 3 V to 3.6 V

產品類別：: 先進先出

出廠包裝數量：: 160

子類別：: 內存和數據存儲

單位重量：: 0.009690 oz

Tags: SN74V21, SN74V2, SN74V, SN74, SN7

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74V215-10PAG 評級和評論

D***n

Great. It came quickly, soldering is excellent. Works

2019-05-09

E**c

Ok.

2019-03-13

SN74V215-10PAG 描述

***p One Stop Global: FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 64-Pin TQFP Tray

***as Instruments: 512 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70

***et Europe: FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 64-Pin TQFP

***i-Key: IC SYNC FIFO MEM 512X18 64-TQFP

***et: 512 X 18, 100MHZ FIFO

***ark: FIFO Logic IC; Frequency Max:133MHz; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Package/Case:64-TQFP; No. of Pins:64; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes ;RoHS Compliant: Yes

***AS INSRUMENTS: The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast as 5 ns. These DSP-Sync FIFO memories feature read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data communications.

***ASI: These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE)\ input controls the 3-state output.

***AS INSTRUMENT: The synchronous FIFOs have two fixed flags, empty flag/output ready (EF\/OR\) and full flag/input ready (FF\/IR\), and two programmable flags, almost-empty (PAE)\ and almost-full (PAF)\. The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD)\. A half-full flag (HF)\ is available when the FIFO is used in a single-device configuration.

***AS: Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and standard mode.

***AS INSTRUMENT: In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A read enable (REN)\ does not have to be asserted for accessing the first word.

***INS: In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.

***AS INSRUMENT: These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI\ and XO\ pins are used to expand the FIFOs. In depth-expansion configuration, first load (FL)\ is grounded on the first device and set to high for all other devices in the daisy chain.

***AS INSTRUMEN: The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.

Market price

型號	描述	庫存	價格
SN74V215-10PAG DISTI # 296-9894-ND	IC SYNC FIFO MEM 512X18 64-TQFP RoHS: Compliant Min Qty: 160 Container: Tray	Temporarily Out of Stock	160:$17.1116
SN74V215-10PAG DISTI # SN74V215-10PAG	FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 64-Pin TQFP - Trays (Alt: SN74V215-10PAG) RoHS: Compliant Min Qty: 160 Container: Tray	Americas - 0	160:$16.5900 320:$16.1900 640:$15.5900 960:$15.1900 1600:$14.8900
SN74V215-10PAG DISTI # SN74V215-10PAG	FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 18 64-Pin TQFP (Alt: SN74V215-10PAG) RoHS: Not Compliant Min Qty: 1	Europe - 0	1:€15.6900 10:€14.9900 25:€14.1900 50:€13.5900 100:€12.9900 500:€12.3900 1000:€11.8900
SN74V215-10PAG DISTI # 595-SN74V215-10PAG	FIFO 512 x 18 Synchronous FIFO Memory RoHS: Compliant	0	1:$20.9900 10:$19.3000 25:$18.3000 100:$16.3000 250:$15.5000 500:$14.5000
SN74V215-10PAG	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64 RoHS: Compliant	4948	1000:$13.1600 500:$13.8500 100:$14.4200 25:$15.0400 1:$16.1900

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