CD40192BPWE4

CD40192BPWE4
Mfr. #:
CD40192BPWE4
描述:
Counter ICs CMOS Presettable BCD Up/Down Counter
生命週期:
製造商新產品
數據表:
CD40192BPWE4 數據表
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更多信息:
CD40192BPWE4 更多信息 CD40192BPWE4 Product Details
產品屬性
屬性值
製造商:
德州儀器
產品分類:
計數器 IC
RoHS:
Y
安裝方式:
貼片/貼片
包裝/案例:
TSSOP-16
計數器類型:
十年
邏輯系列:
CMOS
計數方法:
同步
計數順序:
上/下
工作電源電壓:
3 V to 18 V
最低工作溫度:
- 55 C
最高工作溫度:
+ 125 C
打包:
管子
工作溫度範圍:
- 55 C to + 125 C
品牌:
德州儀器
產品類別:
計數器 IC
出廠包裝數量:
1
子類別:
計數器 IC
單位重量:
0.006102 oz
Tags
CD40192BP, CD40192, CD4019, CD401, CD40, CD4
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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***ser
Logic - Counters CMOS Presettable BCD Up/Down Counter
***i-Key
IC UP/DOWN COUNTR PRESET 16TSSOP
***as Instruments
CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY\ and BORROW\ signals are high with the counter is counting up or down. The CARRY\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\ and CARRY\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package. The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
型號 描述 庫存 價格
CD40192BPWE4
DISTI # CD40192BPWE4-ND
IC UP/DOWN COUNTR PRESET 16TSSOP
RoHS: Compliant
Min Qty: 1800
Container: Tube
Limited Supply - Call
    CD40192BPWE4
    DISTI # 595-CD40192BPWE4
    Counter ICs CMOS Presettable BCD Up/Down Counter
    RoHS: Compliant
    0
      圖片 型號 描述
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      全新原裝
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      全新原裝
      可用性
      庫存:
      Available
      訂購:
      1500
      輸入數量:
      CD40192BPWE4的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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