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SN74ABT853DBRE4

SN74ABT853DBRE4
Mfr. #:
SN74ABT853DBRE4
描述:
Bus Transceivers 8 to 9-Bit Parity Bus Transceivers
生命週期:
製造商新產品
數據表:
SN74ABT853DBRE4 數據表
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ECAD Model:
更多信息:
SN74ABT853DBRE4 更多信息 SN74ABT853DBRE4 Product Details
產品屬性
屬性值
製造商：
德州儀器
產品分類：
總線收發器
RoHS：
Y
邏輯系列：
74ABT
輸入電平：
TTL
輸出電平：
TTL
輸出類型：
3-State
高電平輸出電流：
- 32 mA
低電平輸出電流：
64 mA
傳播延遲時間：
4.8 ns
電源電壓 - 最大值：
5.5 V
電源電壓 - 最小值：
4.5 V
最低工作溫度：
- 40 C
最高工作溫度：
+ 85 C
包裝/案例：
SSOP-24
打包：
捲軸
功能：
帶有奇偶校驗器的總線收發器
高度：
1.95 mm
長度：
8.2 mm
電路數量：
1
產品：
雙CMOS
靜態電流：
24 mA
技術：
雙CMOS
寬度：
5.3 mm
品牌：
德州儀器
安裝方式：
貼片/貼片
通道數：
8
電源電流 - 最大值：
38 mA
工作電源電壓：
4.5 V to 5.5 V
極性：
同相
產品類別：
總線收發器
出廠包裝數量：
1
子類別：
邏輯 IC
單位重量：
0.059966 oz
Tags
SN74ABT853DB, SN74ABT853D, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INVERT 24SSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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 FIFO 512 x 18 x 2 bidir ASynch FIFO Memory
可用性
庫存:
Available
訂購:
5000
輸入數量:
SN74ABT853DBRE4的當前價格僅供參考，如果您想獲得最優惠的價格，請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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