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74ALVCH16600DLG4

74ALVCH16600DLG4
Mfr. #:
74ALVCH16600DLG4
描述:
Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
生命週期:
製造商新產品
數據表:
74ALVCH16600DLG4 數據表
交貨:
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ECAD Model:
更多信息:
74ALVCH16600DLG4 更多信息 74ALVCH16600DLG4 Product Details
產品屬性
屬性值
製造商：
德州儀器
產品分類：
總線收發器
RoHS：
Y
邏輯系列：
74AL
輸入電平：
LVTTL
輸出電平：
LVTTL
輸出類型：
3-State
高電平輸出電流：
- 24 mA
低電平輸出電流：
24 mA
傳播延遲時間：
6.8 ns
電源電壓 - 最大值：
3.6 V
電源電壓 - 最小值：
1.65 V
最低工作溫度：
- 40 C
最高工作溫度：
+ 85 C
包裝/案例：
SSOP-56
打包：
管子
功能：
通用總線收發器
高度：
2.59 mm
長度：
18.41 mm
電路數量：
1
產品：
CMOS
技術：
CMOS
寬度：
7.49 mm
品牌：
德州儀器
安裝方式：
貼片/貼片
通道數：
18
電源電流 - 最大值：
40 uA
工作電源電壓：
1.65 V to 3.6 V
極性：
同相
產品類別：
總線收發器
出廠包裝數量：
1
子類別：
邏輯 IC
觸發類型：
負邊緣
單位重量：
0.024508 oz
Tags
74ALVCH16600D, 74ALVCH16600, 74ALVCH1660, 74ALVCH166, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56
***i-Key
IC UNIV BUS TXRX 18BIT 56SSOP
***eco
18-BIT UBT W/CLK ENABLE
***el Nordic
Contact for details
***as Instruments
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16600 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA\, and CLKENBA\. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
型號 描述 庫存 價格
74ALVCH16600DLG4
DISTI # 74ALVCH16600DLG4-ND		IC UNIV BUS TXRX 18BIT 56SSOP
RoHS: Compliant
Min Qty: 120
Container: Tube		Limited Supply - Call
    74ALVCH16600DLG4
    DISTI # 595-74ALVCH16600DLG4    		Bus Transceivers 18-Bit Univ Bus Trncvr W/3-St Otpt
    RoHS: Compliant    		0
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      Mfr.#: 74ALVCH16244TX

      OMO.#: OMO-74ALVCH16244TX-ON-SEMICONDUCTOR

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      Mfr.#: 74ALVCH16646APA

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      		 全新原裝
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      Mfr.#: 74ALVCH16841DGGS

      OMO.#: OMO-74ALVCH16841DGGS-NEXPERIA

      		 Latches 20-Bit Bus Interface D-Type, Latch
      可用性
      庫存:
      Available
      訂購:
      5500
      輸入數量:
      74ALVCH16600DLG4的當前價格僅供參考，如果您想獲得最優惠的價格，請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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