SN74LS173ADRE4

SN74LS173ADRE4
Mfr. #:
SN74LS173ADRE4
描述:
Flip Flops 4-Bit D-type Reg With 3-State Outputs
生命週期:
製造商新產品
數據表:
SN74LS173ADRE4 數據表
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ECAD Model:
更多信息:
SN74LS173ADRE4 更多信息 SN74LS173ADRE4 Product Details
產品屬性
屬性值
製造商:
德州儀器
產品分類:
人字拖
RoHS:
Y
電路數量:
1
邏輯系列:
74LS
邏輯類型:
D型寄存器
極性:
同相
輸入類型:
單端
輸出類型:
單端
傳播延遲時間:
30 ns
高電平輸出電流:
- 2.6 mA
低電平輸出電流:
24 mA
電源電壓 - 最小值:
4.75 V
電源電壓 - 最大值:
5.25 V
最低工作溫度:
0 C
最高工作溫度:
+ 70 C
安裝方式:
貼片/貼片
包裝/案例:
SOP-16
打包:
捲軸
功能:
D型總線接口
高度:
1.58 mm
長度:
9.9 mm
寬度:
3.91 mm
品牌:
德州儀器
通道數:
4
輸入行數:
2
輸出線數:
1
工作電源電壓:
4.75 V to 5.25 V
產品類別:
人字拖
重置類型:
主復位
出廠包裝數量:
1
子類別:
邏輯 IC
單位重量:
0.023492 oz
Tags
SN74LS173ADR, SN74LS173AD, SN74LS173, SN74LS17, SN74LS1, SN74LS, SN74L, SN74, SN7
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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 16SOIC
***eco
4-BIT D-TYPE REGISTER WITH 3-STATE<AZ
***ark
Flip-Flop Logic IC; Logic Family:LS; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Package/Case:16-SOIC; No. of Pins:16; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The '173 and 'LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G\1, G\2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of -55C to 125C. The SN74173 and SN74LS173A are characterized for operation from 0C to 70C.
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可用性
庫存:
Available
訂購:
4000
輸入數量:
SN74LS173ADRE4的當前價格僅供參考,如果您想獲得最優惠的價格,請提交查詢或直接發送電子郵件至我們的銷售團隊[email protected]
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