MC100LVEL39DWG

Mfr. #:: MC100LVEL39DWG
製造商:: ON Semiconductor
描述:: Clock Generators & Support Products 3.3V ECL Clock Generator
生命週期:: 製造商新產品
數據表:: MC100LVEL39DWG 數據表
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HTML Datasheet:: MC100LVEL39DWG Datasheet MC100LVEL39DWG Datasheet (P4-P6)
ECAD Model:

產品屬性
屬性值

製造商：: 安森美半導體

產品分類：: 時鐘發生器和支持產品

RoHS：: Y

最低工作溫度：: - 40 C

最高工作溫度：: + 85 C

安裝方式：: 貼片/貼片

包裝/案例：: SOIC-20 Wide

打包：: 管子

品牌：: 安森美半導體

產品類別：: 時鐘發生器

出廠包裝數量：: 38

子類別：: 時鐘和定時器 IC

單位重量：: 0.028254 oz

Tags: MC100LVEL39, MC100LVEL3, MC100LVEL, MC100L, MC100, MC10, MC1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

MC100LVEL39DWG 描述

***ser: Amplifiers- Audio 3.3V ECL Clock Generator

***i-Key: IC CLOCK GEN ECL 2/4 4/6 20SOIC

***th Star Micro: The MC100LVEL39 is a low skew 2/4 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. In addition by using the VBB output a sinusoidal source can be AC coupled into the device. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock therefore all associated specification limits are referenced to the negative edge of the clock input. Upon startup the internal flip-flops will attain a random state; therefore for systems which utilize multiple LVEL39s the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39 the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.

Market price

型號	製造商	描述	庫存	價格
MC100LVEL39DWG DISTI # MC100LVEL39DWGOS-ND	ON Semiconductor	IC CLOCK GEN ECL 2/4 4/6 20SOIC RoHS: Compliant Min Qty: 38 Container: Tube	Limited Supply - Call
MC100LVEL39DWG DISTI # 863-MC100LVEL39DWG	ON Semiconductor	Clock Generators & Support Products 3.3V ECL Clock Generator RoHS: Compliant	0
MC100LVEL39DWG	ON Semiconductor	Low Skew Clock Driver, 100LVEL Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20 RoHS: Compliant	305	1000:$4.2200 500:$4.4500 100:$4.6300 25:$4.8300 1:$5.2000

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