SN74ABT7819A-10PH

Mfr. #:: SN74ABT7819A-10PH
描述:: FIFO 512x18x2 Clocked Bidir Mem
生命週期:: 製造商新產品
數據表:: SN74ABT7819A-10PH 數據表
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產品屬性
屬性值

製造商：: 德州儀器

產品分類：: 先進先出

RoHS：: N

包裝/案例：: QFP-80

品牌：: 德州儀器

安裝方式：: 貼片/貼片

產品類別：: 先進先出

出廠包裝數量：: 1

子類別：: 內存和數據存儲

單位重量：: 0.061338 oz

Tags: SN74ABT7819A-1, SN74ABT7819A, SN74ABT781, SN74ABT7, SN74AB, SN74A, SN74, SN7

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Vacuum Packaging with PL

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Anti-Static Bag

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Packaging Boxes

SN74ABT7819A-10PH 描述

***i-Key: IC SYNC FIFO MEM 512X18X2 80-QFP

***as Instruments: A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7819A is a high-speed, low-power, BiCMOS, bidirectional, clocked FIFO memory. Two independent 512 18 dual-port SRAM FIFOs (FIFOA, FIFOB) on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag. The SN74ABT7819A is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The state of the A0A17 outputs is controlled by the port-A chip select (CSA)\ and the port-A write/read select (W/R\A). When both CSA\ and W/R\A are low, the outputs are active. The A0A17 outputs are in the high-impedance state when either CSA\ or W/R\A is high. Data is written to FIFOAB from port A on the low-to-high transition of the port-A clock (CLKA) input when CSA\ is low, W/R\A is high, the port-A write enable (WENA) is high, and the port-A input-ready (IRA) flag is high. Data is read from FIFOBA to the A0A17 outputs on the low-to-high transition of CLKA when CSA\ is low, W/R\A is low, the port-A read enable (RENA) is high, and the port-A output-ready (ORA) flag is high. The state of the B0B17 outputs is controlled by the port-B chip select (CSB)\ and the port-B write/read select (W/R\B). When both CSB\ and W/R\B are low, the outputs are active. The B0B17 outputs are in the high-impedance state when either CSB\ or W/R\B is high. Data is written to FIFOBA from port B on the low-to-high transition of the port-B clock (CLKB) when CSB\ is low, W/R\B is high, the port-B write enable (WENB) is high, and the port-B input-ready (IRB) flag is high. Data is read from FIFOAB to the B0B17 outputs on the low-to-high transition of CLKB when CSB\ is low, W/R\B is low, the port-B read enable (RENB) is high, and the port-B output-ready (ORB) flag is high. The setup- and hold-time constraints for the chip selects (CSA\, CSB)\ and write/read selects (W/R\A, W/R\B) enable write and read operations on memory and are not related to the high-impedance control of the data outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the data outputs. The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOAB (IRA) and the output-ready flag of FIFOBA (ORA). CLKB synchronizes the status of the input-ready flag of FIFOBA (IRB) and the output-ready flag of FIFOAB (ORB). When the IR flag of a port is low, the FIFO receiving input from the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high) again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs. The SN74ABT7819A is characterized for operation from 0C to 70C.

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