AS4C512M16D3LB-12BCNTR

Mfr. #:: AS4C512M16D3LB-12BCNTR
製造商:: Alliance Memory
描述:: DRAM 8G - Dual Die Package (DDP) -12 512M x 16 1.35V(1.283-1.45V) 800MHz DDR3-1600bps/pin Commercial (Extended) (0 95 C) 96-ball FBGA
生命週期:: 製造商新產品
數據表:: AS4C512M16D3LB-12BCNTR 數據表
交貨:: DHL FedEx Ups TNT EMS
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ECAD Model:
更多信息:: AS4C512M16D3LB-12BCNTR 更多信息

產品屬性
屬性值

製造商：: 聯盟記憶

產品分類：: 動態隨機存取存儲器

RoHS：: Y

類型：: SDRAM - DDR3L

數據總線寬度：: 16 bit

組織：: 512 M x 16

包裝/案例：: FBGA-96

內存大小：: 8 Gbit

最大時鐘頻率：: 800 MHz

電源電壓 - 最大值：: 1.45 V

電源電壓 - 最小值：: 1.283 V

電源電流 - 最大值：: 122 mA

最低工作溫度：: 0 C

最高工作溫度：: + 95 C

系列：: AS4C512M16D3LB-12

打包：: 捲軸

品牌：: 聯盟記憶

安裝方式：: 貼片/貼片

濕氣敏感：: 是的

產品類別：: 動態隨機存取存儲器

出廠包裝數量：: 2000

子類別：: 內存和數據存儲

Tags: AS4C512M16D3LB, AS4C512M1, AS4C5, AS4C, AS4

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

AS4C512M16D3LB-12BCNTR 更多信息

DDR3 Synchronous DRAM: Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM: Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

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