CY14V101QS-SF108XI

Mfr. #:: CY14V101QS-SF108XI
製造商:: Cypress Semiconductor
描述:
生命週期:: 製造商新產品
數據表:: CY14V101QS-SF108XI 數據表
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ECAD Model:
更多信息:: CY14V101QS-SF108XI 更多信息 CY14V101QS-SF108XI Product Details

產品屬性
屬性值

Tags: CY14V101QS-SF, CY14V101QS-S, CY14V101QS, CY14V101Q, CY14V101, CY14V10, CY14V1, CY14V, CY14, CY1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CY14V101QS-SF108XI 描述

***S: nvSRAM, 1Mb, QSPI, Up to 108MHz, 2.7/3.6V, SOIC(16), -40°C to 85°C, Tube

***ow.cn: NVRAM NVSRAM Serial-SPI 1Mbit 3V 16-Pin SOIC W Tube

***ark: NV SRAM, 128K X 8BIT, SOIC-16 ROHS COMPLIANT: YES

***ress Semiconductor SCT: Nonvolatile SRAM, 1024 Kb Density, SOP-16, RoHS

***et: 1MB NVSRAM WITH A QUAD SERIAL PERIPHERAL INTERFACE

CY14V101QS-SF108XI 更多信息

CY14V101 1-Mb Quad SPI nvSRAM: Cypress Semiconductor CY14V101 1-Mbit (128K × 8) Quad SPI nvSRAM couples a 1-Mbit nvSRAM with a QPI interface. The QPI enables writing and reading of the memory in either a single (one I/O channel for one bit per clock cycle), dual (two I/O channels for two bits per clock cycle), or quad (four I/O channels for four bits per clock cycle) through the use of specific opcodes. The memory is organized as 128Kbytes each consisting of SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide storage of data. Data transfers from SRAM to the nonvolatile cells (STORE operation) occur automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile cells (RECALL operation). Users may also initiate the STORE and RECALL operations through SPI instructions.Learn More

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