AD9250 Dual ADC

By Analog Devices Inc 169

AD9250 Dual ADC

Analog Devices' AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.

The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs, supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations and a duty-cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high-speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided. Flexible power-down options allow significant power savings, when desired. Programmable over-range level detection is supported for each channel via the dedicated fast detect pins. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface. The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

  • Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC
  • The configurable JESD204B output block supports up to 5 Gbps per lane
  • An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock
  • Support for an optional RF clock input eases system board design
  • Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz
  • Operation from a single, 1.8 V power supply
  • Standard serial port interface (SPI) supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over-range fast detection, and serial output configuration
  • Diversity radio systems
  • Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers
  • I/Q demodulation systems
  • Smart antenna systems
  • Electronic test and measurement equipment
  • RADAR receivers
  • COMSEC radio architectures
  • IED detection/jamming systems
  • General-purpose software radios
  • Broadband data applications