Zynq® UltraScale+™ MPSoC

By Xilinx Inc 677

Zynq® UltraScale+™ MPSoC

Xilinx's Zynq UltraScale+ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Built on a common real-time processor and programmable logic equipped platform, three distinct variants include dual application processor (CG) devices, quad application processor and GPU (EG) devices, and video codec (EV) devices, creating unlimited possibilities for applications such as 5G Wireless, next generation ADAS, and Industrial Internet of Things (IIoT).

The ZCU102 evaluation kit enables designers to jumpstart designs for automotive, industrial, video, and communications applications. This kit features a Zynq UltraScale+ MPSoC device with a quad-core Arm® Cortex®-A53, dual-core Cortex-R5 real-time processors, and a Mali-400 MP2 graphics processing unit based on Xilinx's 16 nm FinFET+ programmable logic fabric. The ZCU102 supports all major peripherals and interfaces enabling development for a wide range of applications.

Zynq® UltraScale+™ MPSoC Product Tables and Product Selection Guide

Zynq UltraScale+ Features ZCU102 Evaluation Kit Features
  • Innovative Arm+ FPGA architecture for differentiation, analytics and control
  • Extensive OS, middleware, stacks, accelerators, and IP ecosystem
  • Multiple levels of hardware and software security
  • Integration delivering the de facto all programmable platform
  • Up to 5X system level performance per watt over Zynq-7000 SoCs
  • Architected to deliver lowest system power
  • Most flexible and scalable platform for maximum reuse and best TTM
  • Industry leading design tools, C/C++, open CL design abstractions
  • Largest portfolio of SW and HW design tools and reference designs
  • Optimized for quick application prototyping with Zynq Ultrascale+ MPSoC
  • DDR4 SODIMM - 4 GB 64-bit with ECC attached to processor subsystem (PS)
  • DDR4 component - 512 MB 16-bit attached to programmable logic (PL)
  • PCIe root port Gen2x4, USB3, display port, and SATA
  • 4x SFP+ cages for Ethernet
  • 2x FPGA mezzanine card (FMC) interfaces for I/O expansion including 16 x 16.3 Gb/s
  • GTH transceivers and 64 user defined differential I/O signals