By Microsemi SoC 82


The ProASICPLUS family of FPGA’s from Microsemi is a second-generation family of Flash field programmable gate arrays (FPGAs) offering enhanced performance over ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). ProASICPLUS devices combine the advantages of ASICs with the benefits of FPGAs, enabling engineers to leverage their existing ASIC or FPGA design flows and tools. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power-up (LAPU). No external boot PROM is required to support device programming. While on-board security mechanisms prevent access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades.

ProASICPLUS devices offer in-system programming capabilities. To program a device, the configuration data is supplied through a standard JTAG interface either from a microprocessor, Silicon Sculptor 3, and FlashPro. For applications without a microprocessor, Silicon Sculptor II is best for production volumes while the FlashPro programmers, with their small size and ease of portability, are ideal for prototyping. The ProASICPLUS family of FPGAs is fully supported by both the Microsemi Libero® IDE and the Microsemi Designer FPGA Development software. Microsemi's Designer software provides a comprehensive suite of backend development tools for FPGA development which includes timing-driven place-and-route, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design.

  • Commercial and industrial
    • 75,000 to 1 million system gates
    • 27 K to 198 Kbits of two-port SRAM
    • 66 to 712 user I/Os
  • Reprogrammable Flash technology
    • 0.22 µm 4 LM Flash-based CMOS process
    • LAPU level 0 support
    • Single-chip solution
    • No configuration device required
    • Retains programmed design during power-down/up cycles
    • Mil/aero devices operate over full military temperature range
  • Performance
    • 3.3 V, 32-bit PCI, up to 50 MHz (33 MHz over military temperature)
    • Two integrated PLLs
    • External system performance up to 150 MHz
  • Unique clock conditioning circuitry
    • PLL with flexible phase, multiply/divide, and delay capabilities
    • Internal and/or external dynamic PLL configuration
    • Two LVPECL differential pairs for clock or data inputs
  • Secure programming
    • The industry’s most effective security key (FlashLock®)
  • Low power
    • Low impedance Flash switches
    • Segmented hierarchical routing structure
    • Small, efficient, configurable (combinatorial or sequential) logic cells
  • Standard FPGA and ASIC design flow
    • Flexibility with choice of industry-standard front-end tools
    • Efficient design through front-end timing and gate optimization
  • ISP support
    • In-system programming (ISP) via JTAG port
  • High-performance routing hierarchy
    • Ultra-fast local and long-line network
    • High-speed very long-line network
    • High-performance, low skew, splittable global network
    • 100% routability and utilization